The PCI-SIG (Special Interest Group) continues to push bandwidth limits.
: The protocol is split into a Transaction Layer , Data Link Layer , and Physical Layer . This separation allows the physical electrical components to evolve (e.g., doubling bandwidth) without requiring massive changes to how software communicates with hardware.
PCIe communication occurs over , which consist of two differential signaling pairs (one for transmit, one for receive). What is PCI Express (PCIe)? – How it Works? - Synopsys pci express specification
The PCIe specification faces physical challenges as speeds increase. At Gen5 and Gen6, signal integrity becomes extremely sensitive to motherboard trace routing, connector quality, and even the material of the printed circuit board. Short trace lengths and low-loss materials are mandatory. Moreover, power consumption and heat dissipation at 64 GT/s are non-trivial concerns for mobile and data-center environments.
The spec defines aggressive power saving states (ASPM - Active State Power Management), allowing devices to enter low-power standby modes when idle to save electricity and reduce heat. The PCI-SIG (Special Interest Group) continues to push
Looking ahead, the PCI-SIG (the standards body) has already announced , targeting 128 GT/s per lane (roughly 16 GB/s per lane, or 128 GB/s for a x16 slot). This will likely require advanced equalization techniques and possibly optical interconnects for longer distances. As AI models grow to trillions of parameters and in-memory databases consume terabytes of RAM, PCIe will remain the critical conduit—the circulatory system of the computer—evolving to ensure that data can flow as fast as it can be processed.
: The highest layer, responsible for generating and receiving Transaction Layer Packets (TLPs). It handles requests like memory reads/writes and configuration cycles. PCIe communication occurs over , which consist of
Unlike the older PCI standard, which used a parallel bus architecture, PCIe uses a serial point-to-point architecture, allowing for higher clock speeds and more efficient data transfer.
The PCIe specification defines a layered architecture consisting of three distinct logical layers:
This layered approach means that higher-level protocols (like NVMe for SSDs or CXL for coherent memory) can run seamlessly over the PCIe transport layer.