Student: Vivado

So, your professor just dropped the bomb: "For this lab, you will be using Xilinx Vivado."

Yes, Vivado is huge. No, you probably don't need the "Full Installation." vivado student

module counter( input clk, input rst, input en, output reg [3:0] count ); So, your professor just dropped the bomb: "For

Click "Run Implementation." This figures out where to physically put your logic on the die. // Sequential Logic Block always @(posedge clk) begin

This report details the design, implementation, and simulation of a 4-bit synchronous binary up-counter using Xilinx Vivado Design Suite. The design utilizes Verilog Hardware Description Language (HDL) to model flip-flops and combinational logic. The objective is to create a counter that increments on the rising edge of a clock signal, includes an active-high enable signal, and a synchronous reset functionality. Simulation results confirm the design meets the required logic specifications.

// Sequential Logic Block always @(posedge clk) begin if (rst) begin count <= 4'b0000; // Synchronous Reset end else if (en) begin count <= count + 1; // Increment counter end end

From "Where is the compile button?" to "Look, my LED blinked!" – Your roadmap to mastering FPGA design.