: While version 1.2 supported up to 2.5 Gbps per lane, version 2.x increases this limit to 4.5 Gbps per lane when using equalization.
| Feature | v1.2 | v2.0 | |--------------------------|--------------------------|------------------------------| | Max data rate | 1.5 Gbps | 2.5 Gbps | | Non-continuous clock | Optional | Improved support | | LP termination | Not specified | Better control | | Skew tolerance | Moderate | Tighter for 2.5 Gbps | | ULPS exit timing | Fixed | More flexible | | Power savings | Basic | Enhanced LP state handling | mipi d phy 2.0 specification
The specification defines three primary operating modes to balance performance and power savings: i.MX 8/RT MIPI DSI/CSI-2 - NXP Semiconductors : While version 1
D-PHY is a interface (except for the bidirectional LPDT option). It uses 1 clock lane + 1 to 4 data lanes . | Feature | Clock Lane | Data Lane
| Feature | Clock Lane | Data Lane | |------------------|------------------------------------|------------------------------------| | Direction | Unidirectional (Master to Slave) | Configurable (Bidirectional opt.) | | Operation in HS | DDR clock (freq = bitrate/2) | DDR data aligned to clock edges | | LP states | Same as data lanes | Same as data lanes | | Special features | Continuous or non-continuous clock | HS-0/1 + LP states + Escape |