| Pin Name | Pin Number(s) | Description | |----------|--------------|-------------| | | Multiple (e.g., A2, B2, C2 …) | Main CPU core power (~0.9V–1.5V) | | VDD_SOC | Multiple (e.g., G1, H1) | SoC voltage (memory controller, Infinity Fabric) | | VDD18 | A1, B1, maybe others | 1.8V standby rail | | PWR_OK | C1 | Power good signal from PSU | | RESET# | D1 | Reset (active low) | | SVI2_SCLK | E1 | SVI2 clock (power management bus) | | SVI2_SDATA | F1 | SVI2 data | | CLK_SLOW | J1 | Slow clock for debug | | PROCHOT# | K2 | Processor hot indicator | | LCLK | L1 | Link clock to chipset | | LDT_RX[0..15] | Various | Infinity Fabric lanes to chipset |
The AM4 platform provides direct PCIe lanes from the CPU to peripherals.
The 1,331 pins are organized into specific groups that handle power delivery, data transmission, and system management. am4 pinout
One of the most complex aspects of the AM4 pinout is the "Combo" nature of the socket. AMD utilized the same physical pin layout for APUs (with integrated graphics) and CPUs (without integrated graphics).
If you need a (e.g., “What pin is VDD_SOC on AM4?”), please provide the motherboard or CPU model, as actual routing varies. For most repair or modding purposes, board-level schematics are required. | Pin Name | Pin Number(s) | Description
The AM5 socket (Ryzen 7000+) uses an LGA design and has a completely different pinout. The following applies only to AM4 (PGA – Pin Grid Array).
The AM4 socket's introduction significantly impacted the CPU market by offering consumers a broad range of processor options across different price points, from budget-friendly Ryzen 3 models to the high-end Ryzen 9 and Threadripper series. This competition has driven innovation and price competitiveness, pushing the boundaries of what consumers can expect from their CPUs. AMD utilized the same physical pin layout for
AM4 CPUs (except APUs) provide PCIe lanes:
These pins provide a return path for current and a ground reference voltage. Hundreds of VSS pins are distributed across the socket to reduce impedance and minimize "ground bounce" in high-speed circuits.
